A buck converter is the most basic SMPS topology. It is widely used throughout the industry to convert a higher input voltage into a lower output voltage. The buck converter (voltage step-down converter) is a nonisolated converter, hence galvanic isolation between input and output is not given.Image below will change on mouse over:
Show below is a buck converter represented as two switches S1 and S2, inductor L1 and capacitor C1. S1 and S2 open and close alternately so that the voltage applied to L1 is either VIN or zero. DC output voltage is then the average voltage applied to L1. If t1 is the time S1 is closed, and t2 is the time it is open, VOUT is equal to:
VIN x TON VO = ----------- = VIN x Duty Cycle (DC) T
Note that the definition of duty cycle allows only for values
between 0 and 1. The formula for VOUT therefore shows a
basic property of buck converters; the output voltage is
always less than the input voltage.
Diodes may be used to replace switches when unidirectional current flow exists. In Figures b and c (above), singleswitch buck regulators are shown with diodes used to replace S2. Diodes cause some loss in efficiency, but simplify the design and reduce cost. Notice that when S1 is closed, D1 is reverse biased (off) and that when S1 opens, the current flow through L1 forces the diode to become forward biased (on). This duplicates the alternate switching action of two switches. There is an exception to this condition, however. If the load current is low enough, the current through L1 will drop to zero sometime during S1 off-time. This is known as discontinuous mode operation. Buck regulators will be in discontinuous mode for any load current less than;
Discontinuous mode alters the original statement that output voltage depends only on input voltage and switch
duty cycle because a third state of the switches now exists with diodes replacing S2; namely both switches off.
Waveforms for voltage and current of S1, D1, L1, C1 and the input source are shown for both continuous and
discontinuous modes of operation.
Normally it is not important to avoid discontinuous mode operation at light load currents. A possible exception to this would be when the “on” time of S1 cannot be reduced to a low enough value to prevent the lightly loaded output from drifting unregulated high. If this occurs, most switching regulators will begin “dropping cycles” wherein S1 does not turn on at all for one or more cycles. This mode of operation maintains control of the output, but the subharmonic frequencies generated may be unacceptable in certain situations
Sown below a single-pole single-throw switch in the form of a transistor Q1, is in series with the DC input Vdc. It is closed for a time To, out of the switching period T. When it is on, the voltage at V1 is Vdc,(assuming for the moment the "on" drop across Q1 is zero). When it is open, the voltage a t V1 falls very rapidly to ground and would have gone dangerously negative had it not been caught and held at ground by the so-called free-wheeling or clamp diode Dl.Image below will change on mouse over:
Assume for the moment that the "on" drop of diode D1 is zero also.
Then the voltage at V1 (Fig. 1.4b)is rectangular, ranging between Vdc
and ground with a "high" time of To,. The average or DC value of this
voltage is Vdc Ton / T. The LoCo filter is added in series between V1 and
Vo and yields a clean, ripple-free DC voltage a t Vo whose magnitude is Vdc Ton / T.
Now Vo is sensed by sampling resistors R1, R2 and compared to a reference voltage VREF in the error amplifier (EA). The amplified DC error voltage Vea is fed to a pulse-width-modulator (PWM) which is essentially a voltage comparator. Another input to the PWM is a sawtooth of period T and usually 3V in amplitude (Vt). The PWM voltage c omparator generates a rectangular waveform (Vwm) which goes high at the start of the triangle and low at the instant the triangle crosses the DC voltage level of the error-amplifier output. The PWM output pulse width To, is thus proportional to the EA amplifier output DC voltage level.
The PWM output pulse is fed to a current amplifier and used to control the "on" time of switch transistor Q1 in a negative-feedback loop.
The phasing is such that if Vdc goes slightly high, the EA DC level goes closer to the bottom of the PWM triangle, the triangle crosses the EA output level earlier in time and the Q1 on time decreases, bringing Vo = Vdc Ton / T back down. Similarly, if Vdc goes low by a certain percentage, the on time increases by the same percentage to maintain Vo constant. The Q1 on time is controlled so as to make the sampled output VoR2(R1 + R2) always equal to the reference voltage Vref.
Assuming 1V voltage drop across D1 and Q1, the DC lossed of the switching regulator are:
AC losses are Q1 turnon and turnoff conduction losses. At the beginning of turnon voltage and current start moving simultaneously and reach their endpoints simultaneously. Current goes from 0 to I, and voltage across Q1 goes from a maximum of Vdc to zero. The average power during this switching time is:
The power averaged over one complete period is:
Assuming the same scenario of simultaneous starting and ending points of the current fall and voltage rise waveforms at the turnoff transition, voltage/current overlap dissipation at this transition is given by:
This power averaged over one complete cycle is:
Assuming Ton = Toff = Ts, total switching losses (the sum of turnoff and turnon losses) are Pac = (Vdc Io Ts)/ 3T and efficiency is:
If a worst-case scenario-as shown above, which is closer to reality-is assumed, efficiencies are lower.
It is assumed that at turnon, the voltage across the transistor remains at its maximum value (Vdc) until the on-turning current reaches its maximum value of Io. Then voltage starts falling, and to a close approximation, current rise time Tcr will equal voltage fall time. Turnon switching losses will then be