MSP430 Tutorial


MSP430x552x Demo Code

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 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
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 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
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 * for an API functional library-approach to peripheral configuration.
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//******************************************************************************
// MSP430x552x Demo - COMPB interrupt capability; Vcompare is compared against 
//                    internal 1.5V reference
//
// Description: Use CompB and internal reference to determine if input'Vcompare'
//    is high of low.  For the first time, when Vcompare exceeds the 1.5V internal
//	  reference, CBIFG is set and device enters the CompB ISR. In the ISR CBIES is
//	  toggled such that when Vcompare is less than 1.5V internal reference, CBIFG is set.
//    LED is toggled inside the CompB ISR
//                                                   
//                 MSP430x552x
//             ------------------                        
//         /|\|                  |                       
//          | |                  |                       
//          --|RST      P6.0/CB0 |<--Vcompare            
//            |                  |                                         
//            |            P1.0  |--> LED 'ON'(Vcompare>1.5V); 'OFF'(Vcompare<1.5V)
//            |                  | 
//
//   Bhargavi Nisarga
//   Texas Instruments Inc.
//   April 2009
//   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>
volatile unsigned int count = 0;
volatile unsigned int i;

int main(void)
{
	WDTCTL = WDTPW + WDTHOLD;     // Stop WDT
	P2DIR |= BIT0;                // P2.0/LED output direction
	P2DIR |= BIT2;
	P7DIR |= BIT4;
	// Setup ComparatorB
	/*
	 * CBCTL0 Register:
	 * The negative terminal of the comparator is disconnected from the input pins
	 * CBIMEN:  0b = Selected analog input channel for V- terminal is disabled.
	 * CBIMSEL: N/A because the negative terminal of the comparator is disconnected from the input pins
	 * CBIPEN:  1b = Selected analog input channel for V+ terminal is enabled
	 * CBIPSEL: Channel input selected for the V+ terminal of the comparator if CBIPEN is set to 1.
	 *
	 * CBCTL1 Register:
	 * CBMRVS: 0b = Comparator output state selects between VREF0 or VREF1
	 * CBMRVL: NA. This bit is valid if CBMRVS is set to 1.
	 * CBON:   1b
	 *
	 * CBCTL2 Register
	 * CBREFACC: 0b = Static mode
	 * CBREFL:   11b = 2.5 V
	 *
	 *
	 *
	 *
	 * #define CBRSEL                 (0x0020)       // Comp. B Reference select
	 */

	/*
	 * CBCTL0 = 0b0000 0000 1000 0000
	 * 15 - 	CBIMEN -  0b = Selected analog input channel for V- terminal is disabled.
	 * 14 - 12	Reserved
	 * 11 - 8 	CBIMSEL - 0h = Channel input selected for the V- terminal of the comparator if CBIMEN is set to 1.
	 * 7 		CBIPEN  - 1b
	 * 6 - 4	Reserved
	 * 3 - 0	Channel input selected for the V+ terminal of the comparator if CBIPEN is set to 1.
	 */
	  CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0. (0x0080) + (0x0000) = (0x0080) - 0b0000 0000 1000 0000
	  /*
	   * CBCTL1 = 0b0000 0001 0000 0000
	   * 15 - 13	Reserved
	   * 12		CBMRVS - 0b = Comparator output state selects between VREF0 or VREF1.
	   * 11		CBMRVL - 0b = VREF0 is selected if CBRS = 00, 01, or 10.
	   * 10		CBON = 0b. This bit turns the comparator on. When the comparator is turned off the Comp_B consumes no power. 0b = Off
	   * 9 - 8	CBPWRMD = 01b = Normal mode (optional)
	   * 7 - 6	CBFDLY = 00b = Typical filter delay of 450 ns. Filter delay. The filter delay can be selected in 4 steps. See the device-specific data sheet for details.
	   * 5		CBEX = 0b0 = Exchange. This bit permutes the comparator 0 inputs and inverts the comparator 0 output.
	   * 4		CBSHORT = 0b = Inputs not shorted. Input short. This bit shorts the + and – input terminals.
	   * 3		CBIES = 0b = 0b = Rising edge for CBIFG, falling edge for CBIIFG
	   * 2		CBF = 0b = Comp_B output is not filtered. Output filter.
	   * 1		CBOUTPOL = 0b = Noninverted. Output polarity. This bit defines the CBOUT polarity.
	   * 0		CBOUT = Output value. This bit reflects the value of the Comp_B output. Writing this bit has no effect on the comparator output.
	   */
	  CBCTL1 |= CBPWRMD_1;          // normal power mode (0x0100)
	  /*
	   * CBCTL2 = 0b 0000 0000 0010 0000
	   * 15		CBREFACC = 0b = Static mode. Reference accuracy. A reference voltage is requested only if CBREFL > 0.
	   * 14	- 13CBREFL = 00b = Reference voltage is disabled. No reference voltage is requested. (01b = 1.5 V, 10b = 2.0 V, 11b = 2.5 V)
	   * 12 - 8	CBREF1 = Reference resistor tap 1. This register defines the tap of the resistor string while CBOUT = 1.
	   * 7 - 6	CBRS = 00b = No current is drawn by the reference curcuitry. Reference source. This bit define if the reference voltage is derived from VCC or
	   * 		from the precise shared reference
	   * 5		CBRSEL = 1b = When CBEX = 0: V(REF) is applied to the – terminal; When CBEX = 1: V(REF) is applied to the + terminal
	   * 4 - 0	CBREF0 = Reference resistor tap 0. This register defines the tap of the resistor string while CBOUT = 0
	   */
	  CBCTL2 |= CBRSEL;             // VREF is applied to -terminal (0x0020)
	  //CBRS_3 =  11 CBREFL_1 = 01
	  //CBCTL2 |= CBRS_3 + CBREFL_1;   		 // R-ladder off; bandgap ref voltage (1.2V)
	                                 	 	 // supplied ref amplifier to get Vcref=1.5V (CBREFL_2)


	  /*
	   *
	   */
	  CBCTL2 |= CBRS_2 + CBREFL_2 + CBREF0_7;// (0x0080) + (0x4000) + (0x0007)
						// R-ladder ON; bandgap ref voltage (2.0V)
						// supplied ref amplifier to get Vcref=2.0V (CBREFL_2)
						// Comp. B Int. Ref.0 Select 7 : 8/32: 2.0 * 8 /32 = 0.50



	  CBCTL3 |= BIT0;               // Input Buffer Disable @P6.0/CB0

	  __delay_cycles(75);           // delay for the reference to settle

	  CBINT &= ~(CBIFG + CBIIFG);   // Clear any errant interrupts
	  CBINT  |= CBIE;               // Enable CompB Interrupt on rising edge of CBIFG (CBIES=0)
	  CBCTL1 |= CBON;               // Turn On ComparatorB

	  for (count = 0; count< 10; count++){
		  P2OUT ^= BIT2;
		  for(i=10000;i>0;i--);
	  }

	while(1){
		 /*
		  * The main difference between the two constructions is that __bis_SR_register()
		  * allows you to set more than just the GIE bit, while __enable_interrupt() only sets GIE bit.
		  */
		 //while(1){
		P2OUT = 0;
		__bis_SR_register(LPM4_bits + GIE);       // Enter LPM4 with inetrrupts enabled
		__no_operation();                         // For debug

		 //__bis_SR_register(CPUOFF);
		 //__delay_cycles(75);           // delay for the reference to settle

	}

}

// Comp_B ISR - LED Toggle
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=COMP_B_VECTOR
__interrupt void Comp_B_ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(COMP_B_VECTOR))) Comp_B_ISR (void)
#else
#error Compiler not supported!
#endif
{
  CBCTL1 ^= CBIES;              // Toggles interrupt edge
  CBINT &= ~CBIFG;              // Clear Interrupt flag
  P2OUT ^= BIT0;                // Toggle LED on P2.0  
  if (count < 100)
	  count++;
  else{
	  P2OUT ^= BIT2;				// Toggle LED on P2.2
	  count = 0;
  }
  
	// __bic_SR_register_on_exit
	__bis_SR_register_on_exit(LPM4_bits + GIE);
	//__bic_SR_register_on_exit(CPUOFF);
}